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843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 1 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary g eneral d escription the ics843252-04 is a 10gb/12gb ethernet clock generator and a member of the hiperclocks tm family of high performance devices from ics. the ics843252-04 can synthesize 10 gigabit ethernet and 12 gigabit ethernet with a 25mhz crystal. it can also generate sata and 10gb fibre channel reference clock frequencies with the appropriate choice of crystals. the ics843252-04 has excellent phase jitter performance and is packaged in a small 16-pin tssop, making it ideal for use in systems with limited board space. f eatures ? two differential 3.3v lvpecl output ? crystal oscillator interface designed for 18pf parallel resonant crystals ? crystal input frequency range: 19.33mhz - 30mhz ? output frequency range: 145mhz - 187.5mhz ? vco frequency range: 580mhz - 750mhz ? rms phase jitter at 156.25mhz (1.875mhz - 20mhz): 0.39ps (typical) ? 3.3v operating supply ? 0c to 70c ambient operating temperature ? industrial temperature information available upon request ? available in both standard and lead-free compliant packages hiperclocks? ic s pulldown pulldown pulldown pullup pulldown 1 0 1 0 phase detector vco 580mhz-750mhz osc 0 = 25 (default) 1 = 30 div. n 4 d le q xtal_in xtal_out q0 nq0 q1 nq1 freq_sel b lock d iagram p in a ssignment c onfiguration t able with 25mh z c rystal s t u p n i y c n e u q e r f t u p t u o ) z h m ( n o i t a c i l p p a y c n e u q e r f l a t s y r c ) z h m ( k c a b d e e f e d i v i d y c n e u q e r f o c v ) z h m ( e d i v i d t u p t u o n 5 20 30 5 74 5 . 7 8 1t e n r e h t e t i b a g i g 2 1 5 25 25 2 64 5 2 . 6 5 1t e n r e h t e t i b a g i g 0 1 c onfiguration t able with s electable c rystals s t u p n i y c n e u q e r f t u p t u o ) z h m ( n o i t a c i l p p a y c n e u q e r f l a t s y r c ) z h m ( k c a b d e e f e d i v i d y c n e u q e r f o c v ) z h m ( e d i v i d t u p t u o n 0 20 30 0 64 0 5 1a t a s 5 2 . 1 20 35 . 7 3 64 5 7 3 . 9 5 1l e n n a h c e r b i f t i b a g i g 0 1 4 25 20 0 64 0 5 1a t a s 5 . 5 25 25 . 7 3 64 5 7 3 . 9 5 1l e n n a h c e r b i f t i b a g i g 0 1 0 35 20 5 74 5 . 7 8 1t e n r e h t e t i b a g i g 2 1 clk_sel ref_clk npll_sel oe nq1 q1 v cco oe npll_sel v cco q0 nq0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 xtal_in xtal_out v ee ref_clk clk_sel v cc v cca freq_sel ics843252-04 16-lead tssop 4.4mm x 5.0mm x 0.92mm package body g package top view the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specifications without notice.
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 2 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary t able 2. p in c haracteristics t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 11 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d 6 , 3v o c c r e w o p. s n i p y l p p u s t u p t u o 4e ot u p n ip u l l u p . t u p n i k c o l c w o l l o f s t u p t u o k c o l c , h g i h n e h w . e l b a n e t u p t u o . h g i h d e c r o f e r a s t u p t u o x q n , w o l d e c r o f e r a s t u p t u o x q , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5l e s _ l l p nt u p n in w o d l l u p . r e d i v i d e h t o t t u p n i s a k c o l c e c n e r e f e r d n a l l p e h t n e e w t e b s t c e l e s . k c o l c e c n e r e f e r s t c e l e s , h g i h n e h w . l l p s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8 , 70 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d 9l e s _ q e r ft u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f 0 1v a c c r e w o p. n i p y l p p u s g o l a n a 1 1v c c r e w o p. n i p y l p p u s e r o c 2 1l e s _ k l ct u p n in w o d l l u p , h g i h n e h w . s t u p n i l a t s y r c s t c e l e s , w o l n e h w . t u p n i t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k l c _ f e r s t c e l e s 3 1k l c _ f e rt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c e c n e r e f e r 4 1v e e r e w o p. n i p y l p p u s e v i t a g e n 6 1 , 5 1 , t u o _ l a t x n i _ l a t x t u p n i , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 3 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary t able 3a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c t able 3c. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 89c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 3b. lvcmos/lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i , k l c _ f e r , l e s _ k l c , l e s _ q e r f l e s _ l l p n v c c v = n i v 5 6 4 . 3 =0 5 1a e o v c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i , k l c _ f e r , l e s _ k l c , l e s _ q e r f l e s _ l l p n v c c v , v 5 6 4 . 3 = n i v 0 =5 -a e o v c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v i c c t n e r r u c y l p p u s r e w o p 0 6a m i a c c t n e r r u c y l p p u s g o l a n a 1 1a m i e e t n e r r u c y l p p u s r e w o p 0 8a m
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 4 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary t able 5. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c t able 4. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 3 3 . 9 10 3z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 5 4 15 . 7 8 1z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n : e g n a r n o i t a r g e t n i @ z h m 5 2 . 6 5 1 z h m 0 2 - z h m 5 7 8 . 1 9 3 . 0s p : e g n a r n o i t a r g e t n i @ z h m 5 7 3 . 9 5 1 z h m 0 2 - z h m 5 7 8 . 1 8 3 . 0s p : e g n a r n o i t a r g e t n i @ z h m 5 . 7 8 1 z h m 0 2 - z h m 5 7 8 . 1 8 3 . 0s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o d b ts p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 4s p c d oe l c y c y t u d t u p t u o 0 5% . n o i t c e s s i h t g n i w o l l o f s t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m o c c . 2 / . n o i t c u d o r p n i d e t s e t t o n . n o i t a z i r e t c a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h t : 3 e t o n
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 5 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary p arameter m easurement i nformation o utput s kew o utput r ise /f all t ime 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v 0.165v clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% q0, q1 nq0, nq1 v ee v cc, v cca, v cco rms p hase j itter phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t sk(o) nqy qy nqx qx o utput d uty c ycle /p ulse w idth /p eriod
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 6 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary a pplication i nformation figure 2. c rystal i npu t i nterface c rystal i nput i nterface the ics843252-04 has been characterized with 18pf paral- lel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843252-04 pro- vides separate power supplies to isolate any high switch- ing noise from the outputs to the internal pll. v cc , v cca, and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. the 10 resistor can also be replaced by a ferrite bead. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc c1 22p x1 18pf parallel crystal c2 22p xtal_out xtal_in
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 7 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary t ermination for 3.3v lvpecl o utput the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminat- ing resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin i nputs : c rystal i nput : for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. ref_clk i nput : for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the ref_clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 8 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843051. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843051 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 80ma = 277.2mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power _max (3.465v, with all outputs switching) = 277.2mw + 60mw = 337.2mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 81.8c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.337w * 81.8c/w = 97.6c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 16 l ead tssop, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard t est boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 9 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 3. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 3. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 8 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary r eliability i nformation t ransistor c ount the transistor count for ics843252-04 is: 2210 t able 6. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard t est boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 9 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary p ackage o utline - g s uffix for 16 l ead tssop t able 7. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
843252ag-04 www.icst.com/products/hiperclocks.html rev. a january 25, 2006 10 integrated circuit systems, inc. ics843252-04 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary t able 8. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademarks, hiperclocks and femtoclocks are trademarks of integrated circuit systems, inc. or its subsidiari es in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 4 0 - g a 2 5 2 3 4 8 s c i4 0 a 2 5 2 3 4p o s s t d a e l 6 1e b u tc 0 7 o t c 0 t 4 0 - g a 2 5 2 3 4 8 s c i4 0 a 2 5 2 3 4p o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l 4 0 - g a 2 5 2 3 4 8 s c il 4 0 a 2 5 2 3p o s s t " e e r f - d a e l " d a e l 6 1e b u tc 0 7 o t c 0 t f l 4 0 - g a 2 5 2 3 4 8 s c il 4 0 a 2 5 2 3p o s s t " e e r f - d a e l " d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n

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